Talk:DEC Alpha
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"Suppressed instructions"
[edit]The Design Principles section talks about "Suppressed instructions", but that doesn't seem to be a technical term. Should that be predication? (Even then, a source is missing to back up the claim that the lack of predication is related to multiple instruction issue, clock rate or multiprocessing.) Nbgl (talk) 03:24, 16 January 2023 (UTC)
- It might refer to an instruction in a delay slot being nullified. For example, a conditional branch instruction might have a delay slot, with a bit in the branch instruction indicating that the instruction in the delay slot should only be executed if the branch is taken, as per this blog post. If the branch is not taken, the instruction in the delay slot is said to be "nullified". (That blog post is wrong when it indicates that the nullification bit in SPARC is unconditional; SPARC's conditional branch instructions also have a "nullify the delay slot instruction if the branch is not taken" bit, not an "always nullify the delay slot instruction" bit.)
- Alpha doesn't have that because Alpha doesn't have delay slots. Guy Harris (talk) 06:52, 16 January 2023 (UTC)
- Yeah, Richard Sites' Digital Technical Journal paper on Alpha says so:
The Alpha AXP architecture has no suppressed instructions, whereby the execution of one instruction conditionally suppresses a following one.
- When I did a Google search for "suppressed instructions", the first set of results had some stuff not relevant to computer instructions, a bunch of hits for Alpha, and a collection of other stuff, such as suppressing speculatively executed instructions that turned out not to be "executed in reality". So it appears to be a word used in some technical contexts, although the use for Alpha appear to be a use for which other terms, such as "nullified instructions", are used for the same concept with other instruction sets. Guy Harris (talk) 08:07, 16 January 2023 (UTC)
Memory semantics
[edit]DEC Alpha is notorious for being particularly "weak", in the sense of requiring particular inter-thread synchronisation that is implied by other architectures, in a trade-off between implied synchronisation (easier for programmers) and potential performance (when comparing ideal implementations), with PA-RISC at the other end of the spectrum. There seems to be an opportunity for somebody with specific knowledge to describe this issue where it seems to belong, to help make sense of C++ memory_order_consume. If you are that person, you need no further explanation. RFST (talk) 06:51, 16 September 2024 (UTC)